The present invention relates to a method of fabricating a semiconductor device and a semiconductor device fabricated thereby and, more particularly, to a method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby.
Attempts to increase device integration density in microelectronic integrated circuits typically result in the fabrication of devices of continually decreased size and increased density. In order to provide electrical access to these devices, conventional techniques to photolithographically define the location of contact holes to these devices have also had to improve. Such improvements have typically included the development of photolithographic alignment techniques having reduced tolerances. Reduction of contact hole size may not represent an acceptable approach when forming highly integrated devices because reductions in contact hole size typically lead to substantial and unacceptable increases in contact resistance. Techniques to reduce photolithographic alignment tolerances have typically not scaled at the same rate as techniques to scale the size of microelectronic devices. To address this limitation associated with photolithographic alignment, self-aligned contact hole fabrication techniques that are less dependent on photolithographic accuracy have been developed.
A method of forming self-aligned contact hole is disclosed in U.S. Pat. No. 5,763,323, entitled xe2x80x9cMethod for Fabricating Integrated Circuit Devices Including Etching Barrier Layers and Related Structuresxe2x80x9d by Kim et al., which is hereby incorporated herein by reference. According to U.S. Pat. No. 5,763,323, an insulating layer is formed on a substrate and a plurality of parallel conductive lines are formed on the insulating layer. An etch barrier is then formed on each of the parallel conductive lines and contact holes are formed between the etch barriers. The contact holes expose portions of the substrate without exposing the plurality of parallel conductive lines. In particular, the contact holes can be formed by forming a patterned mask layer on the insulating layer and etch barriers, and by etching the exposed portions of the insulating layer. The patterned mask layer selectively exposes a plurality of parallel strips orthogonal to the plurality of parallel conductive lines. Related structures are also disclosed.
In addition, FIGS. 1A to 5A and FIGS. 1B to 5B are cross-sectional views for illustrating a fabrication method of a semiconductor memory device according to conventional technology. Here, FIGS. 1A to 5A are cross-sectional views taken along the line perpendicular to word lines of a DRAM device. Also, FIGS. 1B to 5B are cross-sectional views taken along the line perpendicular to bit lines of a DRAM device. Referring to FIGS. 1A and 1B, an isolation layer 3a is formed on a predetermined region of a semiconductor substrate 1 to define an active region. A plurality of insulated word line patterns are formed on the substrate having the isolation layer 3a. The word line patterns cross over the active region and each of the word line patterns comprises a word line 7 and an insulating capping pattern 9, which are sequentially stacked. A gate oxide layer 5 is interposed between the word line pattern and the substrate having the isolation layer 3a. Impurity regions 13s and 13d are formed at the active region. The impurity region 13d between the word line patterns operates as a common drain region of a cell transistor and the impurity region 13s opposite to the common drain region 13d operates as a source region of a cell transistor. A gate spacer 11 is formed on sidewalls of the word line patterns.
The resulting structure, including the gate spacer 11 is then covered with a conformal etch stop layer 15 such as a silicon nitride layer. After forming the etch stop layer 15, a lower separating layer 17 is formed over an entire surface of the etch stop layer 15. The lower separating layer 17 fills gap regions between the word line patterns. A first photoresist layer is formed on the lower separating layer 15 and is patterned to form a first photoresist pattern 19 defining pad contact holes.
Referring to FIGS. 2A and 2B, the lower separating layer 17 is etched using the first photoresist pattern 19 as a etch mask, to thereby expose a portion of the etch stop layer 15. Subsequently, the exposed etch stop layer 15 is etched to form pad contact holes exposing the common drain region 13d and the source regions 13s. During this etching step, the upper corner regions of the word line patterns can be easily over-etched. Accordingly, deformed insulating capping patterns 9a having convex top surfaces remain on the word lines 7 as shown in FIG. 2A. The narrower the width of the word line patterns, the sharper the remaining top surfaces thereof. In addition, the gate spacer 11 is likewise etched during the etching process for forming the pad contact holes. Thus, a deformed gate spacer 11a is formed. As a result, the thickness of the gate spacer 11 and the insulating capping patterns 9 covering the upper corner region of the word lines 7 is substantially reduced as shown in FIG. 2A. In the meantime, the etching process for forming the pad contact holes results in the formation of a lower separating layer pattern 17a that isolates the adjacent pad contact holes from each other. After removing the first photoresist pattern 19, a doped polysilicon layer 21 is formed on an entire surface of the substrate including the lower separating layer pattern 17a. The doped polysilicon layer 21 completely fills the pad contact holes.
Referring to FIGS. 3A and 3B, the doped polysilicon layer 21 is planarized using a chemical mechanical polishing (CMP) process until the deformed insulating capping patterns 9a are exposed, thereby forming bit line pads 21d and storage node pads 21s on the exposed common drain regions 13d and the exposed source regions 13s respectively. At this time, the deformed insulating capping patterns 9a become further etched. Thus, the word lines 7 can be easily exposed or very thin insulating capping patterns 9axe2x80x2 may exist on the word line 7 as shown in FIG. 3A. This is due to the convex top surfaces of the deformed insulating capping patterns 9a. That is to say, in the event that the top surface of the CMP stopper has a sharp profile, the polishing selectivity is reduced. Therefore, during the CMP process, the top surface of the CMP stopper should be flat in order to increase the polishing selectivity.
An inter-layer insulating layer 23 is then formed on an entire surface of the resultant structure including the bit line pads 21d and the storage node pads 21s. A plurality of bit line patterns are formed on the inter-layer insulating layer 23. Each of the bit line patterns comprises a bit line 25 and an insulating capping pattern 27 which are sequentially stacked. The bit line patterns are formed so that they cross over the word line patterns. Additionally, the respective bit lines 25 are electrically connected to the bit line pads 21d via bit line contact holes (not shown). A bit line spacer 29 is formed on sidewalls of the bit line patterns. An upper separating layer 31 is then formed on an entire surface of the resultant structure, including the bit line patterns and the bit line spacer 29.
Referring to FIGS. 4A and 4B, a second photoresist pattern 33 is formed on the upper separating layer 31. The upper separating layer 31 and the inter-layer insulating layer 23 are sequentially etched using the second photoresist pattern 33 as a etch mask, thereby forming storage node plug contact holes 35 exposing the storage node pads 21s. At this time, even though the insulating capping patterns 27 and the bit line spacer 29 operate as etch stoppers, the insulating capping patterns 27 and the bit line spacer 29 are once again over-etched as shown in FIG. 4B. Accordingly, deformed insulating capping patterns 27a and deformed bit line spacers 29a are formed. Also, each of the deformed insulating capping patterns 27a includes a convex top surface, as in the deformed insulating capping patterns 9a illustrated in FIG. 2A. In particular, in the event that the second photoresist pattern 33 is shifted along the direction parallel to the bit lines 25, for example due to misalignment, the thin insulating capping patterns 9axe2x80x2 may be easily etched away. In which case, the word lines 7 can be exposed by the storage node plug contact holes 35.
Referring to FIGS. 5A and 5B, after removing the second photoresist pattern 33, a conductive layer such as a doped polysilicon layer is formed on an entire surface of the resultant structure where the second photoresist pattern 33 is removed. The conductive layer is planarized using the CMP process to form storage node plugs 37 inside the storage node plug contact holes. At this time, the deformed insulating capping patterns 27a are further polished during the CMP process. Thus, the bit lines 25 may be exposed, or very thin insulating capping patterns 27axe2x80x2 may remain on the bit lines 25.
As described above, the conventional technology may still be prone to reliability problems when photolithographic alignment techniques having relatively large alignment tolerances are used. Thus, not withstanding such self-alignment techniques, there continues to be a need for improved methods of forming highly integrated memory devices and related structures.
It is therefore a feature of the invention to provide a method of forming a semiconductor memory device, which is capable of increasing a polishing selectivity during the CMP process.
It is another feature of the invention to provide a method of forming a semiconductor memory device, which is capable of increasing an alignment margin during the photolithographic process.
It is still another feature of the invention to provide a method of forming a semiconductor memory device, which is capable of increasing reliability.
It is yet another feature of the invention to provide a reliable semiconductor memory device.
These features can be provided by a method of forming a semiconductor memory device and a semiconductor memory device formed thereby. In the method and device, double layered capping pattern is used to improve the polishing selectivity and the dishing problem during the CMP process for planarization. In particular, the double layered capping pattern comprises an insulating capping pattern and a conductive capping pattern which are sequentially stacked on an interconnection line.
According to one aspect of the invention, the method includes the step of forming a plurality of interconnection patterns on a semiconductor substrate. Each of the interconnection patterns comprises an interconnection line and a double layered capping pattern which are sequentially stacked. The double layered capping pattern comprises a first capping pattern and a second capping pattern which are sequentially stacked. In particular, the second capping pattern is formed of a material layer having a high etching selectivity with respect to an insulating layer such as a silicon oxide layer. For example, the second capping pattern may be formed of a conductive layer such as a silicon layer. The substrate having the plurality of interconnection patterns is then covered with a planarized separating layer and a sacrificial layer. The planarized separating layer fills gap regions between the interconnection patterns and the sacrificial layer is formed of a material layer having an etching selectivity (preferably, a wet etching selectivity) with respect to the planarized separating layer.
The sacrificial layer and the planarized separating layer are successively patterned to form a hole exposing at least a predetermined region of the semiconductor substrate between the interconnection patterns which are adjacent to each other. At this time, even though a portion of the second capping pattern is exposed during the patterning process, it can prevent the first capping pattern from being etched or exposed by the hole. The hole is then filled with a conductive pattern. After forming the conductive pattern, the sacrificial layer is selectively removed. Accordingly, the conductive pattern is relatively protruded upward. A planarization process such as CMP process is carried out on the protruded conductive pattern and the second capping patterns, thereby forming a conductive plug and exposing the first capping patterns.
In addition, in the event that the semiconductor substrate includes a cell array region and a peripheral region having a relatively low pattern density compared with the cell array region, interconnection pattern extensions, which are extended from the interconnection patterns, may be formed in the peripheral region. Thus, each of the interconnection pattern extensions has the same structure as the interconnection pattern. Also, the planarized separating layer can be formed by forming a separating layer on the entire surface of the resultant structure having the interconnection patterns and the interconnection pattern extensions and planarizing the separating layer until the top surface of the interconnection patterns in the cell array region are exposed. Here, an insulating layer having a superior filling characteristic, e.g., a high density plasma (HDP) oxide layer is an attractive candidate as the separating layer. In this case, the interconnection pattern extensions in the peripheral region may be still covered with the planarized separating layer, even though the interconnection patterns in the cell array region are exposed by the planarization process. As a result, the second capping patterns in the peripheral region may be left even after forming the conductive plug.
According to another aspect of the invention, the semiconductor memory device comprises a semiconductor substrate including a cell array region and a peripheral region having a relatively low pattern density as compared with the cell array region. A plurality of deformed interconnection patterns are disposed in the cell array region of the semiconductor substrate. Also, a plurality of interconnection pattern extensions are disposed in the peripheral region of the semiconductor substrate. Each of the deformed interconnection patterns includes an interconnection line and a first capping pattern which are sequentially stacked. Unlike this, each of the interconnection pattern extensions includes an interconnection line extension, a first capping pattern and a second capping pattern which are sequentially stacked. Here, the interconnection line may be a bit line of the memory device. Sidewalls of the deformed interconnection patterns and the interconnection pattern extensions are covered with spacers formed of an insulating layer.
The semiconductor memory device may further comprise a planarized separating layer that covers the peripheral region including the interconnection pattern extensions. Also, the semiconductor memory device may further comprise conductive plugs formed in predetermined gap regions between the deformed interconnection patterns and separating layer patterns interposed between the conductive plugs.